Optimal Systolic Block Size for Low Power High Speed Digital Filters Based on 3-port Adaptor

Abstarct-Allpass digital lters are major building blocks in many digital lter architectures. In this paper an optimal pipelined architecture for a 2nd order allpass section based on 3-port adaptor is proposed. The architecture has been shown to improve the lter overall performance in term of power-area-speed by 3 times using 1 m CMOS standard cell design and by 5.4 times using custom cells. Given the same clock speed and without the use of supply voltage scaling, the architecture consumes 35% less power than non-pipelined equivalent using custom cell implementation and by 20% using standard cells. With a maximum sampling rate of 185 MHz, the adaptor's power consumption is 1.5 mW, representing a 55% improvement in power/frequency from the non-pipelined standard cell adaptor.